Retention flip-flops are used to retain or keep a state on a circuit line without the need to continuously power and clock the generating circuit. Some digital circuit types that perform logic operations (AND, OR, etc.) require continued power to perform the logic operation. To achieve the computing goals, these circuit types need fast ON/OFF switching times often driving large loads. These goals are typically achieved employing relatively large transistors capable of switching large currents. It is typical to store the digital states of these logic operations in a register flip-flop. In ordinary operation these flip-flops must also drive large loads requiring relatively large transistors.
Retention of an achieved state involves differing considerations. Once a line is switched to a new state the current needed to retain that state is much less than the current needed to quickly achieve the state. Digital circuits often spend more time retaining an achieved state than switching. The electric power requirements of portable, battery powered equipment make reduced power consumption advantageous. If the electronic circuit consume less power, either the battery size can be reduced while retaining the same operating life or the same battery size promotes longer device operating life. This reduced power consumption quest has led to the use of retention flip-flops.
Retention flip-flops are employed to keep or hold the state of a circuit line after switching is completed by the primary circuit. The electrical power required to retain a circuit state is less than the electrical power required to switch to that state. Thus a retention flip-flop keeps the circuit line state while the primary circuit, which uses more electrical power, is switched OFF, not clocked or both. A retention flip-flop typically includes smaller transistor having lower current drive capacity than the transistors in the primary circuit. Thus the circuit state is retained at a lower power cost.
Such a retention flip-flop is often similar to a memory bit cell connected to the retained circuit line. The primary circuit has sufficient current drive capacity to set the state of the retention flip-flop during switching operation. The retention flip-flop retains this state while the primary circuit is turned off.
Recent developments in integrated circuit fabrication have changed the parameters of this engineering compromise. Smaller manufacturing features enable production of integrated circuits with more transistors. This generally supports greater computing power per integrated circuit. This development has led to production of systems on a chip (SOC) for many battery powered equipment. The use of smaller transistors reduces the utility of retention flip-flops. Reduced transistor feature size results in greater relative leakage current. Leakage current flows through a transistor nominally biased OFF. Thus for smaller feature size transistors the retention flip-flops drain a larger share of current relative to the primary circuit than for larger feature size transistors.
The design goal for retention flip-flops in low power SOC designs are: drawing very low leakage current in retention mode; retaining the state when the switchable VDD is powered down; and limited compromise on the active mode timing performance. Conventional existing retention flip-flops employing the lowest leakage transistors having high threshold voltages (HVT) have poor timing performance. Conventional existing retention flip-flops employing standard threshold transistors (SVT) have high retention mode current leakage.